HELP!! HOW TO WIRE 2 .vhd FILES!!!! IN QUARTUS!

Hello,

If I understood, what you have to do is to instantiate your memory from the top file.

You can do it in this way:

entity upro is

port (

clk: in std_logic;

Rst: in std_logic;

R_w: out std_logic;

dir: out std_logic_vector (7 downto 0);

dat: inout std_logic_vector (3 downto 0)

);

end upro;

.

.

.

signal a: std_logic_vector(3 downto 0);

signal carga_a: std_logic_vector(3 downto 0);

signal pc: std_logic_vector(7 downto 0);

signal carga_pc: std_logic_vector(7 downto 0);

signal rdat_in: std_logic_vector(3 downto 0);

signal dat_in: std_logic_vector(3 downto 0);

signal dat_out: std_logic_vector(3 downto 0);

signal rwaux: std_logic;

signal presente: estado:= inicial;

COMPONENT ram256x4 is

port (

Clock: in std_logic;

OE: in std_logic;

RW: in std_logic;

CS: in std_logic;

RW_Addr: in std_logic_vector (7 downto 0); Data_A: inout std_logic_vector (3 downto 0);

Data_B: in std_logic_vector (3 downto 0);

)

END COMPONENT;

ARCHITECTURE ...

BEGIN

TEST_ram256x4 : ram256x4

port map

(

Clock=>Clk,

RW_Addr=>dir,

DATA_A =>dat,

RW=>r_w,

...

);

...

Hope it helps you

DABG