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Hi Gianluca,
i don't exactly understand what's your problem, but when you want to map the pins from the emac0/1 periphals from the hps to the FPGA you have to do the following:
1.) In Qsys you have to edit the hps component. In the periphial pins tab -> EMAC0/1 pin you have to select FPGA. Then generate the HDL Files.
2.) Assign the pins like it is described in AN706.
3.) Run a full compilation
4.) Update the prelaoder section, how do you do this is described at rocketboards
5.) Run the board with the new fpga image
Best regards
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Thank you for your reply.
Yes this is exactly what I have to do. Before start to route the EMAC1 I try with a simple example that consist in drive a HPS_LED from the fpga and this example work properly.
I'm trying to follow the AN706 but I don't understand how I can connect the data from the Triple speed ethernet IP to the emac signal.
In the page 10 of the AN706 on the datasheet it says that these pins pht_txd_o [3: 0] must be connected to PO_TX port [3: 0] but the PO_TX of the TSE IP is also an input. I'm doing something wrong?
Have I to use the triple speed ethernet IP in order to send data on the ethernet?
If you do not pick and use the FPGA from EMAC1 LOANIO function when I perform the synthesis I get an error because some pins, such as the TX or RX are unidirectional, but when I use the LOANIO are inout.
I'm trying different ways, can anyone help?
Best Regards
Gianluca
Honored Contributor
