Help about the connection between IC of voltage 5V and cyclone II

Hi,

I agree with your thoughts and ALTERA in fact points to the problem of unconfigured state (by linking to the chapter of the device handbook). Maybe there were to many problems due to misuse (not observing the problem of unconfigured FPGA connected to 5V driven signals) as this design hint is only stated in Cyclone but not in CycloneII Handbook...

Carlhermann

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use a clock divider for the IO clock.

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Ever I heard a problem about the clock divided by counter in FPGA is not steady enough .Though I've already given up this solution ,I still want to confirm whether I can use the clock divided by counter for devices directly .For this problem ,I have already seen various of opinions on the internet .

"not steady enough" is far from specifying a clear problem I fear.

Generally, didvided clocks can be used as peripheral clock.

There may be problems:

- to achieve a specific timing relation between the divided clock and the system clock when processing the pheripheral input or generating the output signals

- the clock output can have glitches, if it's erroneously sourced by cominational logic rather than a register

- jitter of the FPGA clock tree can be an issue in acquisition of high speed signals

Apart from the latter, the problems can be overcome. The best way to generate a peripheral clock with specified timing is using a PLL clock divider.