Help about the connection between IC of voltage 5V and cyclone II

"not steady enough" is far from specifying a clear problem I fear.

Generally, didvided clocks can be used as peripheral clock.

There may be problems:

- to achieve a specific timing relation between the divided clock and the system clock when processing the pheripheral input or generating the output signals

- the clock output can have glitches, if it's erroneously sourced by cominational logic rather than a register

- jitter of the FPGA clock tree can be an issue in acquisition of high speed signals

Apart from the latter, the problems can be overcome. The best way to generate a peripheral clock with specified timing is using a PLL clock divider.