Honored Contributor
Honored ContributorHi,
A general note(I have no idea what modules you have in hand): The parallel mpeg TS inteface must include video data(8 bits), clock and data_valid. The ASI generator needs all above signals and converts video_data to a serial stream(without clk or data_valid) and uses 8b/10b encoding. The clk has to be recovered by ASI Rx device from data stream. The data_valid is implied through null character insertion, the Rx has to ignore these null characters. Your description of mpeg packet structure and system level diagram has nothing to do with TS signals interface. Documents often don't show low level details except at relevant diagrams.
