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——> A <= C & (B | A);
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Yes, that's the same, although in your original code C signal logic was inverted, namely
A <= ~C & (B | A);
Please note that the above line must be included in a always @(posedge clk) statement.
I guess your concerns are on the difference between assign and always statement.
You'd better refer to a Verilog manual, which is more reliable and detailed than me :p.
Anyway, in a few words:
- this is not C programming; hdl functions are evaluated in parallel, not in a sequential way
- assign dictates an operation to be performed continuously, independently from clock and where the statement is placed; you can place it before or after the always process which needs it, but the result would still be the same. An assign is generally synthesized in a combinatorial logic chain.
- always @(posedge clk) means the following operations are to be executed only when a positive edge is detected on clk signal; this involves use of flip-flops during synthesis.
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