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Altera_Forum
Honored Contributor
Honored ContributorHas anyone successfully inferred read enable ports on true dual-port ram?
The megawizard successfully produces the following true dual-port altsyncram code with read enables:
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ram_dp (
...
Altera_ForumHonored Contributor
Honored Contributorread enables get no mention in any of the templates in the HDL coding styles:
http://www.altera.co.uk/literature/hb/qts/qts_qii51007.pdf I would raise an enhancement request from altera - but dont expect support any time soon. You can work around it by making the read enable control the read_address instead of the data output register. Or just stick with the megawizard function
