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Altera_Forum
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11 years ago

hard reset controller pin(Cyclone V PCIE hard IP)

we use PCIE CvP function of cyclone v device(5CGXFC5C6F27C7N), and have to use the hard reset controller. we are confused with the pin of hard reset controller, according to the user guide, th...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

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Hi Kerb

For your information, the nperst pin mapping for Cyclone V is opposite from Stratix V and Arria V.

Stratix V and Arria V: bottom HIP is associated with nPERSTL0, top HIP is associated with nPERSTL1.

Cyclone : bottom HIP is associated with nPERSTL1, top HIP is associated with nPERSTL0.

When using bottom HIP, assign nPERSTL1 to pin_perstn of the PCIe core is indeed correct.

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Hi skbek,

Thanks! we think so