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clair's avatar
clair
Icon for New Contributor rankNew Contributor
5 years ago

H-tile Hard IP Fitter Failed in Stratix10mx

Error(14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 HSSI_CR2_EHIP_CORE(s)). Fix the errors described in the submessages, and then rerun the Fi...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


I suspect fitter error is just due to some channel pin placement issue and not about Quartus design connection or RTL error.


This is due to once I disable your pin location setting in your Quartus project (let Quartus auto fit pin placement) then fitter compilation can passed.

  • I didn't check all your pin placement vs Quartus compilation passed pin placement yet but at high level I can see that your bank 1F Rx{3:2] location is swap.


I encourage you to do the same like me. Let Quartus auto fit then compare with your original pin location setting then you will figure out which pin placement is causing the problem here


Thanks.


Regards,

dlim


clair's avatar
clair
Icon for New Contributor rankNew Contributor
5 years ago

Hi,

I just set the pin placement as the schematic said. Now I suspect the sdc file about the native phy clk has problems. Which files should I refer to to place the RX_CLK* and TX_CLK* in the right channel?

The sdc in the project is auto generated by the htile IP.

set RX_CLK0 [get_clocks u_0|av_top|alt_ehipc2_0|alt_ehipc2_hard_inst|altera_xcvr_native_inst|g_native_phy_inst[0].s10_xcvr_native_inst|*rx_pcs_x2_clk|ch0]
set RX_CLK1 [get_clocks u_0|av_top|alt_ehipc2_0|alt_ehipc2_hard_inst|altera_xcvr_native_inst|g_native_phy_inst[1].s10_xcvr_native_inst|*rx_pcs_x2_clk|ch0]
set TX_CLK0 [get_clocks u_0|av_top|alt_ehipc2_0|alt_ehipc2_hard_inst|altera_xcvr_native_inst|g_native_phy_inst[0].s10_xcvr_native_inst|*tx_pcs_x2_clk|ch0]
set TX_CLK1 [get_clocks u_0|av_top|alt_ehipc2_0|alt_ehipc2_hard_inst|altera_xcvr_native_inst|g_native_phy_inst[1].s10_xcvr_native_inst|*tx_pcs_x2_clk|ch0]

set RX_CLK2 [get_clocks u_0|av_top|alt_ehipc2_0|alt_ehipc2_hard_inst|altera_xcvr_native_inst|g_native_phy_inst[2].s10_xcvr_native_inst|*rx_pcs_x2_clk|ch0]
set RX_CLK3 [get_clocks u_0|av_top|alt_ehipc2_0|alt_ehipc2_hard_inst|altera_xcvr_native_inst|g_native_phy_inst[3].s10_xcvr_native_inst|*rx_pcs_x2_clk|ch0]
set TX_CLK2 [get_clocks u_0|av_top|alt_ehipc2_0|alt_ehipc2_hard_inst|altera_xcvr_native_inst|g_native_phy_inst[2].s10_xcvr_native_inst|*tx_pcs_x2_clk|ch0]
set TX_CLK3 [get_clocks u_0|av_top|alt_ehipc2_0|alt_ehipc2_hard_inst|altera_xcvr_native_inst|g_native_phy_inst[3].s10_xcvr_native_inst|*tx_pcs_x2_clk|ch0]