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Altera_Forum
Honored Contributor
12 years agoWhich of the 2 solutions are legal for Cyclone IV GX FPGA:
1). connect both unused dedicated reference clock ( REFCLK1n and REFCLK1p ) pins directly to PCB GND plane. 2). connect one unused dedicated reference clock REFCLK1p pin directly to PCB GND plane, but use another one from the pair ( REFCLK1n ) for reference clock. P.S. The question is because I don't have enough space on PCB to place 10 KOhm resistor from unused REFCLK to GND.