GXB 0 PPM core clock setting witn coreclck

Question

i don't arrive to used "GXB 0 PPM core clock setting" in assignement editor.

I want to used only one clock to write in the TxFiFO, and to read the RxFIFO.

I always have the same error:

Error (167028): Input port CORECLK of GXB Receiver channel PCS "MyGx_I_corelclk:inst26|MyGx_I_corelclk_alt4gxb:MyGx_I_corelclk_alt4gxb_component|receive_pcs0"

must be fed by output port CLOCK_OUT of GXB Receiver channel PCS "MyGx_I_corelclk:inst26|MyGx_I_corelclk_alt4gxb:MyGx_I_corelclk_alt4gxb_component|receive_pcs0"

because the GXB receiver is not rate-match FIFO enabled or receiver is operating at a dissimilar data rate to the transmitters or receiver can be dynamically reconfigured.

I don't want to use tx_clkout and rx_clkout to clock tx_datain

[*] and rx_dataout

[*] like in

Stratix IV Device Handbook

Volume 2: Transceivers

Figure 2–37. Sixteen Identical Channels Across Four Transceiver Blocks for Example 8

on page 2.69

l

thanks

altera_forum · Answer

As I understand it, if you do not connect the rx_clkout to the coreclkin pin, Quartus II would flag critical warning instead of error. Just wonder if you have connected any clock ie from a PLL to the coreclkin pins?

altera_forum · Answer

It's ok, if I connect tx_clkout to tx_coreclk, no errors from quartus.

but i want to connect the same clock (Clk200M) who drive the pll_inclk pin to the tx_coreclk pin. this clock as the same frequency that the "tx_clkout",

and it seam possible to drive tx_corelck with this clock (clk200M).

if this schem work, I will make the same connexions for rx_corelck, and for all the others channel.

This schem will allows me to drive all the signals of the GXB with the same clock, without the need

to change clock domains from tx(rx)_ clkout to clk200M.

Here is an image of my design.https://www.alteraforum.com/forum/attachment.php?attachmentid=10923

Thanks

altera_forum · Answer

Hi,

As long as you can ensure that there is 0ppm between your clk200M with the tx/rx_clkout, there should be no issue. The 0ppm warning is to alert user to double check on this to avoid the phase comp FIFO over/under flow.

altera_forum · Answer

Thanks for your response,

I'am sure that there is 0 ppm phase relation between the clocks.

but it's not a warning when Quartus compile the design, it's a FATAL ERROR

and i Am blocked at this point.

altera_forum · Answer

What is the fatal error message? Do you have a chance to try with the latest Quartus II 15.0 to see if error still exist?

Forum Discussion

GXB 0 PPM core clock setting witn coreclck

7 Replies

Recent Discussions

EMIF Pin Assignment for Agilex 7 FPGA I-Series DevKit (DK-DEV-AGI027R1BES)

Vcm for the clock input pins of agilex5 E-series FPGA A5ED065BB32AE5SR0

Timing Slacks inside Altera IP

Part Status request

Agilex 7 DDR4 Reset and ADDR/CMD Clock PCB Implementation Documentation Discrepancy