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HBhat2's avatar
HBhat2
Icon for Contributor rankContributor
5 years ago

GPIO state of ARRIA 10 FPGA during Power up & during configuration

Hi, I want to know whether the GPIOs in the arria 10 GPIO bank remain in High impedance/Tri-state during power up sequencing. Where I can get the information regarding this. Which document clear...
HBhat2's avatar
HBhat2
Icon for Contributor rankContributor
5 years ago

Hi,

Thank you for the response.

1) Before and during configuration, all user I/O pins are tristated.

2) Stratix® series, Arria® series, and Cyclone® series have weak pull-up resistors on the I/O pins
which are on, before and during configuration

I just confused with these 2 points. Point 1) says IO pins are tristated. & point 2 says IOs have weak pull-ups.

My confusion is if weak pull up is connected to IOs before & during configuration, what is the meaning of tristated (point 1)?

Whether this means that the internal IO buffers of FPGA is not connected to the pins (tristated) but FPGA IO pins are pulled up with resistors so that when we physically measure the voltage before or during configuration, we can get VCCIO voltage level?

With regards,

HPB

AminT_Intel's avatar
AminT_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago
Hello,

Tri-state means a state of high impedance. Like example, a pin can be pulled to certain voltage or become high impedance (input) without much current flow.

Another example is on bidirectional serial lines where a pin can be an input and output. This allows the external chip to control its logic level when they are inputs.

Thank you,

Amin