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Altera_Forum
Honored Contributor
Honored Contributorglitch problem...
Hi. I want to know difference between two code , especially glitch problem.
I saw a two examples in the book and the book said first code has a glitch, but second code doesn't have the glitch, and show me the waveform editor picture. why does the book says first code have a glitch, and second code doesn't have the glitch? I want to know the reason why first code has glitch and second doesn't have! first code! LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY ex12_11 is port( ncp,nre : in std_logic; q : buffer integer range 0 to 15); end ex12_11; ARCHITECTURE arc of ex12_11 is begin process(ncp,nre) begin if(nre='0' or q = 10) then q<=0; elsif(ncp'event and ncp='0') then q<=q+1; end if; end process; end arc; second code LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY ex12_12 is port( ncp,nrd : in std_Logic; q : buffer integer range 0 to 15); end ex12_12; ARCHITECTURE arc of ex12_12 is begin process(ncp,nrd) begin if(nrd ='0') then q<=0; elsif(ncp'event and ncp='0') then if(q=10) then q<=0; else q<=q+1; end if; end if; end process; end arc; p.s ( is there any way to find a glitch in model_sim? Is there any button to find glitch? Do I have to zoom in and see all the pulse one by one?)2 Replies
Altera_Forumit will be to do with synthesised logic. The first uses an async reset that means the counter bits will not all got to '0' at exactly the same time, and any logic generated from it will potentially glitch for a short period (in the order of a few ns, or even ps)
the second uses a synchronous reset, which should set all values simultaneously.- Altera_Forum
in the first code the 'q' counter resets itself immediately after reaching '10' value,
the second remains stable in '10' for one clock period and then goes to '00'; j.a
