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Altera_Forum's avatar
Altera_Forum
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12 years ago

Giving stimulus to a VHDL design through an input file for regression testing

Hi, I'm currently doing verification for an FPGA board through ModelSIM For stimulating various test scenarios, I'm creating an array of all possible input values and testing the design by running...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

You need to use the std.textio library. There are many tutorials out there on the web. Get stuck into one of these, and you can post back here for any specific questions you have.