Giving stimulus to a VHDL design through an input file for regression testing

Hi, I'm currently doing verification for an FPGA board through ModelSIM

For stimulating various test scenarios, I'm creating an array of all possible input values and testing the design by running it over a for loop, that selects the i-th input for i-th iteration.

This test bench setup is not flexible, like if we want to add an input, the array declaration, dimension to be changed carefully which takes more time.

To avoid that and also to program the inputs randomly, I found programming the stilmulus through an input file would help.

Please help me on how to program an input value through an input file using a VHDL testbench(or any HDL).

Thanks.