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Altera_Forum
Honored Contributor
Honored ContributorGiving external input to Triple Speed Ethernet
Hello everybody,
I want to modify the tutorial "using Triple Speed Ethernet" according to my requirement. In brief what I used is: Qsys(Hardware Generation), NIOS II Eclipse(ApplicationSoftware: C/C++), Wireshark(to see the output in PC coming through Ethernet Interface) and Networking (Ctr+shift+Alt: to see the Link Speed, which is 770 Mbps). Input is defined within application C/C++ Program in NIOS II Eclipse software as transmitted frame. I would like to know if I have to give continuous data stream from some pins of FPGA (or after some processing in FPGA) as input to ethernet, what should I do? I see Conduit Connection in used tse_mac IP core of Qsys. I also see conduit connection in top level generated verilog code. should I modify the generated verilog code in this top level entity to give input and again compile the program or is there any other method? - Regards FPGA beginner25 Replies
Altera_ForumHi,
If I want to give continuous data stream input from ADC (10 bit) to this "UPD Offload example", then where I have to change in this design? I mean at which component?- Altera_Forum
You would need to change the GEN block. This is the one generating the packet's data payload.
- Altera_Forum
Hi,
Is it compulsory to use External RAM (and thus DDR2 SDRAM controller) in "udp offload example"? I really don't understand the purpose of it in this project. If so, is DDR2 SDRAM controller compatible with Quartus Web edition (Free version) and CycloneIVE or there is some kind of licence stuff? I am asking this because following error occurs on compilation. Error (292019): Core "DDR2 High Performance Controller" (6AF7_00BF) is not enabled for current device family - Altera_Forum
You can use whatever RAM you like (on-chip, off-chip, SRAM, SDRAM, etc.).
The RAM is there so that software (by default iniche) has storage for Ethernet frames. The SGDMA controllers transfer the frames between RAM and Avalon-ST (for the TSE ports). It sounds like you need to change the memory controller to match whatever memory you have in your hardware design. - Altera_Forum
Hi,
To generate PRBS packet, LFSR5 is used for 32 bits but I didn't understand the statement next_value <= ((((next_value << 5) & 32'hFFFFFFE0) | ((next_value >> 27) & 32'h0000001F)) + 32'h33557799); in this program: begin if(go_bit & !running_bit) begin next_value <= initial_value; end else if(((state == DATA_STATE) || (state == EOP_STATE)) && aso_src0_valid && aso_src0_ready) begin next_value <= ((((next_value << 5) & 32'hFFFFFFE0) | ((next_value >> 27) & 32'h0000001F)) + 32'h33557799); end Theory seems to be clear from here http://www1.verigy.com/cntrprod/groups/public/documents/webcontent/cnsmprod_020300.pdf but not the program. could anybody please explain little bit? - Altera_Forum
Hi,
As I need only point to point system (not TCP/IP or UDP), therefore I modified the Tutorial (UDP offload Example) as in attachment. Could anybody please check, if it will be feasible? - Altera_Forum
Yes it will work, as long as your custom GEN module generates a correct Ethernet Header. If you don't have the header, it will be dropped by the receiving end.
As for the line code from your previous message, it does a 5-bit rotation of the generated value on the left, and adds a constant value to the result. The
part shifts the value 5 bits on the left, and the(next_value << 5) & 32'hFFFFFFE0
part gets the 5 most significant bits (that are dropped by the previous shift) and put them back in the 5 low bits of the new value. Those two operations combines do the rotation.(next_value >> 27) & 32'h0000001F) - Altera_Forum
Hi,
I am little bit confused about control signal of DEMUX in the design (attachment above). Because in "UDP offload example", there are 4 channels which is controlled by channel signal coming from "UDP channel mapper component" for DEMUX. But in my case (Point to point system: see attachment above), I just need to distinguish in DEMUX which signal goes to NIOSII Processor and which signal to hardware and I am confused about control signal of DEMUX. Could anybody please explain it? - Altera_Forum
The "control signal of DEMUX" is the Avalon-ST "channel" signal: the DEMUX is simply routing the incoming Avalon-ST packet (your ethernet frame) to the Avalon-ST interface that is indicated by the 'channel' signal.
In the UDP offload example, the "UDP port to channel mapper" is the component which creates the 'channel' information, as it is not something normally part of the TSE output. In this example, it is basically a small lookup on the UDP packet 'port' and if a match is found in the control registers, it sends the packet with the corresponding channel number; otherwise it sends it to channel "4" which will end up with the NIOS software via the SGDMA. This is on or around line 513 of udp_port_to_channel_mapper.v For getting started, I would recommend to continue to use the existing mapper component, but only connect your new component and the NIOS SGDMA ports to the DEMUX. Or, you can copy & modify the original mapper and alter it to only support (2) channels. - Altera_Forum--- Quote Start --- For getting started, I would recommend to continue to use the existing mapper component, but only connect your new component and the NIOS SGDMA ports to the DEMUX. Or, you can copy & modify the original mapper and alter it to only support (2) channels. --- Quote End --- Hi ted! what about the packet format which I have at this point? I have not sent "UDP packet" but just Ethernet packet without IP and UDP Encapsulation. As far I understood in "UDP port to channel mapper" component, It also doing some operation concerning IP and UDP packet.
