Gigabit Transceiver Lane Assignement_5SGXA7KF35

I am using StratixV 5SGXA7KF35 for a Prototype design. In this design, x8 Gigabit Transceivers are used for FPGA to FPGA interconnection. Protocol is not yet defined. It may be any one of the following PCIe, XAUI or Serial Lite.

We are facing crisscross issue in PCB, If i connect (0-0, 1-1, 2-2 , ....) order and same issue exist in lane reversal case(

In this case, Can GXB_TX_R0P/N should be Lane0 or can it be connected to Lane-1, Lane-2, etc.. i.e Can i change the order of Lane assignment.

For example, can i connect like below

FPGA-1 Lane FPGA-2 Lane

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GXB_TX_R0P/N - GXB_RX_R5P/N

GXB_TX_R1P/N - GXB_RX_R6P/N

GXB_TX_R2P/N - GXB_RX_R3P/N

GXB_TX_R3P/N - GXB_RX_R1P/N

GXB_TX_R5P/N - GXB_RX_R2P/N

GXB_TX_R6P/N - GXB_RX_R8P/N

GXB_TX_R7P/N - GXB_RX_R7P/N

GXB_TX_R8P/N - GXB_RX_R0P/N

GXB_TX_R4P/N is unused and assigned for CMU PLL.