get_keepers--non-combinational nodes means ??

Hello,

I know this is probably too late, but perhaps someone else will find use in this.

A node represents a wire carrying a signal that travels between different logical components of a design file.

In Verilog HDL, nodes are called "nets."

"Combinational" refers to the logic type that drives the node.

Combinational logic feeds the node or group, for example, an AND gate.

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Source:

https://www.intel.com/content/www/us/en/programmable/quartushelp/22.3/index.htm#reference/glossary/def_node.htm

https://www.intel.com/content/www/us/en/programmable/quartushelp/22.3/index.htm#reference/glossary/def_nodetype.htm