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sumanth1's avatar
sumanth1
Icon for New Contributor rankNew Contributor
3 years ago

Generating an Agilex per pin RLC IBIS (.ibs) file

Hi, I'm trying to produce an ibis file for my FPGA design using the method outlined in: Generating an Agilex per pin RLC IBIS (.ibs) file (intel.com) I require package-specific RLC data for th...
AqidAyman_Altera's avatar
AqidAyman_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,


Do you have any updates? Did you manage to overcome the error seen previously with the new file?


There is a blog from CadEnhance shares the steps you can try to build the IBIS Model for Intel Agilex. You can see below link, perhaps maybe it can also help you. This is just a suggestion, not a solution from me.


https://www.cadenhance.com/blog/how-can-i-build-an-ibis-model-for-the-new-intel-agilex-fpga-design


Please let me know if you still encountered the error.


Regards,

Aqid