Generating a signal (a VHDL description) with a well-defined frequency in a FPGA

If I understood your system; the ADC samples your sensor and then you have to process it and pass it through DAC to 900MHz.

And that you want to generate a test signal instead of ADC generated signal to test your baseband processing. In that case you don't need vhdl but just a vector(possibly random) generated off chip, filtered to your expected bandwidth and save to ram. Then when testing you need to read the test signal on the appropriate sampling frequency.