Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Generating a 100 MHZ signal on a 50 MHZ board?

I'm justing starting out with FPGA's and am wondering how to generate a 100 MHZ digital signal on a 50 MHZ board? I am using a Cyclone II DE2.

I want the signal to be vaguely digital and correspond to memory reads from an SDRAM. I suspect it is possible to read the SDRAM twice as fast as the 50 MHZ system clock. I want to request data from the SDRAM twice as fast as my system clock of 50 MHZ. Is this possible? Does anybody know of any guides?

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    --- Quote Start ---

    I'm justing starting out with FPGA's and am wondering how to generate a 100 MHZ digital signal on a 50 MHZ board? I am using a Cyclone II DE2.

    --- Quote End ---

    FPGAs have phase-locked loops (PLLs) inside the devices for generating higher or lower clock frequencies. Search for the ALTPLL MegaFunction users guide and read about them there.

    I vaguely recall that the hardware component of the "My First NIOS" tutorial creates an SOPC System (or Qsys system now) that includes a PLL. Read that document too.

    Cheers,

    Dave