Generating a 100 MHZ signal on a 50 MHZ board?

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I'm justing starting out with FPGA's and am wondering how to generate a 100 MHZ digital signal on a 50 MHZ board? I am using a Cyclone II DE2.

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FPGAs have phase-locked loops (PLLs) inside the devices for generating higher or lower clock frequencies. Search for the ALTPLL MegaFunction users guide and read about them there.

I vaguely recall that the hardware component of the "My First NIOS" tutorial creates an SOPC System (or Qsys system now) that includes a PLL. Read that document too.

Cheers,

Dave