Altera_Forum
Honored Contributor
15 years agoGenerate Simulation data from RAM or ROM table and acquire with Signal Tap Analyzer?
I've designed a filter in matlab and generated HDL code and a test bench for this filter and successfully simulated this design in modelsim. i'm trying to verify the results by Programming the design on the Cyclone II FPGA and getting it's output. i'm not sure how to do this i've been told in a different post to acquire simulation data from a RAM or ROM (How? http://www.alteraforum.com/images/smilies/confused.gif ) and acquire with the signal tap analyzer? how do i provide Data input for my filter? and how do i get it's output from the FPGA?
I need as much as help as i can on this process. Any help will be greatly appreciated. One final thought can't i simply use the test bench generated from matlab and program that on the board to verify it's results.