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Honored Contributor
Honored ContributorGenerate programming file for multiple device chain (HDL and Nios code)
I have a board that has two Cyclone IV devices on it. Each Cyclone will have it's own unique HDL and embedded NIOS processor. My question is how do I generate the programming file for the serial co...
Altera_ForumHonored Contributor
Honored ContributorIn the Xilinx world, the FPGA image would contain a block ram that is initialized with reset vectors and boot code for the soft core processor. I'm new to Altera, so I don't know if this is possible here. Assuming it is, then your EPCS would simply have two FPGA images programmed.
