Generate patterns through CPLD(MAXII)?

I mean the DE0 platform with followings. Will this be enough for test pattern generator?

Cyclone III EP3C16F484 with ~16,000 LEs

8MB SDRAM and 4MB Flash

USB Blaster onboard

Is DE0 with CyloneIII suitable for test pattern generator?

Thanks.

Dave, this is very important information to me.

Thanks a lot for the recommendation.

Now, I know what to start with.

Best regards,

Cliff

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I'm new to FPGA/CPLD. Could any one help me?

I'm wondering if I can use CPLD/FPGA to generate some patterns to output pins? This is for some simple test purpose.

For example, under 50MHz clock, to generate pattern as "0011110000111100101010...."

As I know, the CPLD/FPGAs are to be programmed as logic functions.

Appreciate for the answers.

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There are two key differences between FPGAs (eg., Cyclone IV devices) and CPLDs (eg., MAX II devices); the CPLDs have a small number of logic elements and no on-chip RAM.

If you are making a test pattern generator, then I would recommend looking at using a Cyclone III or IV device. The JTAG interface on the device can be used as a 'logic analyzer' (using SignalTap II) so you can see your pattern being generated, and you could wire signals from your device under test back to the FPGA to capture the response.

Since the MAX II does not have RAM, this feature is not available there.

Cheers,

Dave

Thanks for promptly response, Cris!

Then, I will need to study how to implement it through FPGA.

Best regards,

Sure! This is one of the basic purposes of programmable logic.

What you need can be done defining a simple shift register function.