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Altera_Forum
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14 years ago

Generate patterns through CPLD(MAXII)?

I'm new to FPGA/CPLD. Could any one help me? I'm wondering if I can use CPLD/FPGA to generate some patterns to output pins? This is for some simple test purpose. For example, under 50MHz clo...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Is DE0 with CyloneIII suitable for test pattern generator?

Thanks.