Generate patterns through CPLD(MAXII)?

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Before going that far, I need to generate serial patterns for some purpose.

How can I generate serial patterns?

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With a parallel to serial shift register?

Look at the documents on this page:

http://www.ovro.caltech.edu/~dwh/carma_board/ (http://www.ovro.caltech.edu/%7edwh/carma_board/)

http://www.ovro.caltech.edu/~dwh/carma_board/fpga_configuration.pdf (http://www.ovro.caltech.edu/%7edwh/carma_board/fpga_configuration.pdf)

http://www.ovro.caltech.edu/~dwh/carma_board/at84ad001b_tests.pdf (http://www.ovro.caltech.edu/%7edwh/carma_board/at84ad001b_tests.pdf)

http://www.ovro.caltech.edu/~dwh/carma_board/ad9956_tests.pdf (http://www.ovro.caltech.edu/%7edwh/carma_board/ad9956_tests.pdf)

They all have examples of devices with serial interfaces, along with the FSM designs. Just copy something in there.

If you want to generate a long sequence of random bits, then use an LFSR:

http://www.ovro.caltech.edu/~dwh/correlator/pdf/lfsr_tutorial.pdf (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/lfsr_tutorial.pdf)

These sequences are not really random, in that they follow a well defined pattern. You can generate an LFSR serial pattern, capture the first few bits and use that as a seed to a receiver-side LFSR checker. This is how the Altera pattern-generator and pattern-checker cores work.

Cheers,

Dave