Generate-for loop to reset array?

Using Modelsim, I can do this in some module:

...

reg [7:0] ram0 [63:0];

reg [7:0] ram1 [63:0];

reg [7:0] ram2 [63:0];

reg [7:0] ram3 [63:0];

wire strobe;

wire [7:0] addr;

wire [7:0] data;

integer i;

always @(posedge clock or negedge reset)

begin

if (~reset)

begin

for(i=0; i<64; i=i+1)

begin

ram0 <= 8'h0;

ram1 <= 8'h0;

ram2 <= 8'h0;

ram3 <= 8'h0;

end

end

else if (strobe)

case(addr[1:0])

2'h0: ram0[addr[7:2]] <= data;

2'h1: ram1[addr[7:2]] <= data;

2'h2: ram2[addr[7:2]] <= data;

2'h3: ram3[addr[7:2]] <= data;

default:;

endcase

end

...

No problem under Modelsim, and it simulates fine and inits the memory to all zeroes (or whatever I select). Since it can be synthesized with the loop unrolled, the loop should synthesize.

Under Quartus II 9.1, I get a warning about inferred latches on the variable "i". Bracketing the above with generate/endgenerate and/or using genvars just gets me piles of errors.

How, exactly, does one specify this kind of register array init using Quartus. Right now the only way to do this without any flags is to unroll the loop.