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Altera_Forum
Honored Contributor
16 years agoGenerate-for loop to reset array?
Using Modelsim, I can do this in some module: ... reg [7:0] ram0 [63:0]; reg [7:0] ram1 [63:0]; reg [7:0] ram2 [63:0]; reg [7:0] ram3 [63:0]; wire strobe; wire ...
Altera_Forum
Honored Contributor
16 years agoAs I said I am NOT desiring a RAM block. Quite the contrary. I want a register file so that I can read the array via an unclocked mux.