Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Generate-for loop to reset array?

Using Modelsim, I can do this in some module: ... reg [7:0] ram0 [63:0]; reg [7:0] ram1 [63:0]; reg [7:0] ram2 [63:0]; reg [7:0] ram3 [63:0]; wire strobe; wire ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

--- Quote Start ---

You should consider, that introducing a reset action prevents implementation of the register file in internal RAM. A power on reset to zero or a defined content is possible, however.

--- Quote End ---

That is quite the intent. This allows me to clock the register file on the (rare) writes and read it statically. Saves power, FWiW (and in the vanilla-version ASIC I'm modeling, it does matter). I actually intend to use the "strobe" signal as the clock, but simplified it here for clarity.