Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Generate block of verilog

Hi Sir,

I am studying Verilog language. Below is a exercise about 'Generate ' and 'Task'.

The quartus compiler report 'Can't resolve multiple constant drivers for net "tsk.outdata" at test.v(12)' . Could anyone help me?

Thanks.

////////////////

module test(clk,sel,in,out);

input clk;

input sel;

input in;

output [1:0] out;

genvar i;

generate

for(i=0;i<2;i=i+1)

begin: replicate

always @(posedge clk)

begin

tsk(sel,in,out[i]);

end

end

endgenerate

task tsk;

input select;

input indata;

output outdata;

begin

case (select)

0:

outdata=indata;

1:

outdata=outdata;

endcase

end

endtask

endmodule

////////////////

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    18 years ago

    The output variable in the task has a static lifetime. You're basically saying, "If select = 1, then output holds its previous value, e.g. the value you assigned it from the last time select = 0". That is, each call to tsk potentially assigns a value to outdata; hence, there are multiple drivers.

    Admittedly, the tool could generate a more useful error. In theory, it could create a latch for outdata and resolve all possible calls to the task. It's better to avoid this coding style, or declare your task as automatic.