Forum Discussion
Altera_Forum
Honored Contributor
18 years agoGenerate block of verilog
Hi Sir, I am studying Verilog language. Below is a exercise about 'Generate ' and 'Task'. The quartus compiler report 'Can't resolve multiple constant drivers for net "tsk.outdata" at...
Altera_Forum
Honored Contributor
18 years agoThe output variable in the task has a static lifetime. You're basically saying, "If select = 1, then output holds its previous value, e.g. the value you assigned it from the last time select = 0". That is, each call to tsk potentially assigns a value to outdata; hence, there are multiple drivers.
Admittedly, the tool could generate a more useful error. In theory, it could create a latch for outdata and resolve all possible calls to the task. It's better to avoid this coding style, or declare your task as automatic.