Generate a pulse?

Hi Cliffchen,

here is a classic pulse generator for one clock period in vhdl:

edge_detect: process ( reset_n, clk )

begin

if (reset_n = '0') then

ff0 <= '0';

ff1 <= '0';

elsif (clk'event and clk = '1') then

ff0 <= in;

ff1 <= ff0;

end if;

end process edge_detect;

pulse = '1' when (ff0 = '1' and ff1 = '0') else '0';

Now, if the "in" signal changes from '0' to '1' the output "pulse" is '1' for one clock cycle.