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Honored Contributor
Honored ContributorGenerate 1Hz clock from a 50MHz clock
I want to generate 1Hz clock with 50% duty from 40MHZ input clock to MAX II CPLD. I had known to keep the 40MHz clock as input then use the generated 1Hz clk signals from the counter divisions as ...
Altera_ForumHonored Contributor
Honored Contributorghxy00,
you are actually creating ripple clocks in your design, so it is a fair warning you get. You can avoid the ripple clock warning by using the global 50 MHz clock for all cascaded counters and use the carries from the previous chain as enables for the dollwing chain. But if you do that by simple combinatorial logic you will get a slower counter again. That's why I used registered look-ahead carries in my example.
