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Honored Contributor
Honored ContributorGenerate 1Hz clock from a 50MHz clock
I want to generate 1Hz clock with 50% duty from 40MHZ input clock to MAX II CPLD. I had known to keep the 40MHz clock as input then use the generated 1Hz clk signals from the counter divisions as ...
Altera_ForumHonored Contributor
Honored ContributorTo josyb,
Yes, you are probably right, because the overflow value is fixed at compile time, counting up or down should not make a difference. But for other cases it does, so I try to always count down, that way if I latter want to change the design to be a bit more dynamic then I do not have that many changes to make and I still get optimal results.
