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Altera_Forum's avatar
Altera_Forum
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15 years ago

Generate 1Hz clock from a 50MHz clock

I want to generate 1Hz clock with 50% duty from 40MHZ input clock to MAX II CPLD. I had known to keep the 40MHz clock as input then use the generated 1Hz clk signals from the counter divisions as ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

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I wonder why these manufacturing people keep changing things and making our life at field a bit hard.

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Although offered as a "CPLD", MAXII is actually a family of small SRAM based FPGAs with nonvolatile configuration. I assume, it's the only way to achieve a similar logic complexity. I won't expect a typical small CPLD design to be slower with MAX II.

Unfortunately, josyb's test code doesn't work with MAX3000 CPLD, Quartus says to use latches and doesn't give a meaningful timing analysis.