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Honored Contributor
Honored ContributorGenerate 1Hz clock from a 50MHz clock
I want to generate 1Hz clock with 50% duty from 40MHZ input clock to MAX II CPLD. I had known to keep the 40MHz clock as input then use the generated 1Hz clk signals from the counter divisions as ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- kaz, MAXII actually has a LUT-architecture! (see page 2-8 of the MAX II Device Handbook). --- Quote End --- Thanks for letting me know. I wonder why these manufacturing people keep changing things and making our life at field a bit hard. I assume the cpld arhitecture based on sum of produts is meant to be very fast so why did they steal from fpga's LUT??
