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Altera_Forum
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15 years ago

Generate 1Hz clock from a 50MHz clock

I want to generate 1Hz clock with 50% duty from 40MHZ input clock to MAX II CPLD. I had known to keep the 40MHz clock as input then use the generated 1Hz clk signals from the counter divisions as ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

kaz,

MAXII actually has a LUT-architecture! (see page 2-8 of the MAX II Device Handbook).

ghxy00,

The issue with long counters is that even the fast carry chain tends to take longer. Cascading 8-bit lpm counters using a look-ahead register carry-over to the next counter will generate the fastest counter.

Actually I am working on a StratixII GX EP2SGX60F1152-C3 design where I have trouble with a 24 bit counter running at 100 MHz!

So I amused myself a bit and made a small test-project for a (slower) MAXII EPM240ZM68C7 device (see attached .qar). I got 44.98 MHz for a standard LPM based design, and got 102 Mhz for the cascaded LPM version. This comes of course with a price; you will use more LUTs. Design settings were : Analysis set to Speed and fitting to Standard Effort.