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Honored Contributor
Honored ContributorGenerate 1Hz clock from a 50MHz clock
I want to generate 1Hz clock with 50% duty from 40MHZ input clock to MAX II CPLD. I had known to keep the 40MHz clock as input then use the generated 1Hz clk signals from the counter divisions as ...
Altera_ForumHonored Contributor
Honored ContributorI would rather use 25 bits and avoid the analysis of cascaded counters.
You are not counting the overheads of each division which needs a toggle signal per stage as well as logic to detect the max count. note also that cpld hasn't got LUT as fpga
