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Altera_Forum's avatar
Altera_Forum
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16 years ago

gating the output of a clocked register onto pins

I have a simple process in a max 2 that writes and is supposed to read a register array and put the data onto device pins- the same pins I use to write data to the register.

It is really simple:

register_process: process(localclk, reset_pulse, reset_flash, Dcsn)

begin

if localclk'event and localclk = '1' then

if Dwrn = '0' and Dcsn = '0' and Drdn = '1' then

case Daddr(3 downto 0) is

when "0000" => reg0 <= Data(2 downto 0);

when "0010" => reg2(7 downto 0) <= Data(7 downto 0);

when "0011" => reg2(15 downto 8) <= Data(7 downto 0);

when "0100" => reg2(23 downto 16) <= Data(7 downto 0);

when "0101" => reg3 <= Data(7 downto 0);

when "0110" => reg4 <= Data(7 downto 0);

when "0111" => reg5(7 downto 0) <= Data(7 downto 0);

when "1000" => reg5(15 downto 8) <= Data(7 downto 0);

when "1001" => reg5(23 downto 16) <= Data(7 downto 0);

flash_load <= '1';

when "1010" => reg6(7 downto 0) <= Data(7 downto 0);

when "1011" => reg6(15 downto 8) <= Data(7 downto 0);

when "1100" => reg6(23 downto 16) <= Data(7 downto 0);

pulse_flag <= '1';

when others => null;

end case;

elsif Drdn = '0' and Dcsn = '0' and Dwrn = '1' then

case Daddr(3 downto 0) is

when "0000" => Data(2 downto 0) <= reg0;

when "0001" => Data(7 downto 0) <= quad_count;

quad_reset <= '1';

when "0010" => Data <= reg2(7 downto 0);

when "0011" => Data <= reg2(15 downto 8);

when "0100" => Data <= reg2(23 downto 16);

when "1101" => Data <= keys(7 downto 0);

when "1110" => Data(2 downto 0) <= keys(10 downto 8);

when others => null;

end case;

elsif reset_pulse = '1' then

reg6 <= "000000000000000000000000";

elsif reset_flash = '1' then

flash_load <= '0';

else

Data <= "ZZZZZZZZ";

quad_reset <= '0';

end if;

end if;

end process register_process;

The problem is that data is correctly written and I can see it on the Q pins of the ffs but I can't seem to get it back on the device pins.

I know I am forgetting something and I hope someone will just put me out of my misery and tell me what it is.

Thank you,

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    You can use an interim signal set and then gate that set onto the pins external to the process:

    Register_Process: Process(Localclk, Reset_Pulse, Reset_Flash, Dcsn)

    Begin

    If Localclk'Event And Localclk = '1' Then

    If Dwrn = '0' And Dcsn = '0' And Drdn = '1' Then

    Case Daddr(3 Downto 0) Is

    When "0000" => Reg0 <= Data(2 Downto 0);

    When "0010" => Reg2(7 Downto 0) <= Data(7 Downto 0);

    When "0011" => Reg2(15 Downto 8) <= Data(7 Downto 0);

    When "0100" => Reg2(23 Downto 16) <= Data(7 Downto 0);

    When "0101" => Reg3 <= Data(7 Downto 0);

    When "0110" => Reg4 <= Data(7 Downto 0);

    When "0111" => Reg5(7 Downto 0) <= Data(7 Downto 0);

    When "1000" => Reg5(15 Downto 8) <= Data(7 Downto 0);

    When "1001" => Reg5(23 Downto 16) <= Data(7 Downto 0);

    Flash_Load <= '1';

    When "1010" => Reg6(7 Downto 0) <= Data(7 Downto 0);

    When "1011" => Reg6(15 Downto 8) <= Data(7 Downto 0);

    When "1100" => Reg6(23 Downto 16) <= Data(7 Downto 0);

    Pulse_Flag <= '1';

    When Others => Null;

    End Case;

    Elsif Drdn = '0' And Dcsn = '0' And Dwrn = '1' Then

    Case Daddr(3 Downto 0) Is

    When "0000" => Outputsig(2 Downto 0) <= Reg0;

    When "0001" => Outputsig(7 Downto 0) <= Quad_Count;

    Quad_Reset <= '1';

    When "0010" => Outputsig <= Reg2(7 Downto 0);

    When "0011" => Outputsig <= Reg2(15 Downto 8);

    When "0100" => Outputsig <= Reg2(23 Downto 16);

    When "1101" => Outputsig <= Keys(7 Downto 0);

    When "1110" => Outputsig(2 Downto 0) <= Keys(10 Downto 8);

    When Others => Outputsig <= "Xxxxxxxx";

    End Case;

    Elsif Reset_Pulse = '1' Then

    Reg6 <= "000000000000000000000000";

    Elsif Reset_Flash = '1' Then

    Flash_Load <= '0';

    Else

    Data <= "Zzzzzzzz";

    Quad_Reset <= '0';

    End If;

    End If;

    End Process Register_Process;

    Outen <= Not Drdn And Not Dcsn And Dwrn;

    Data <= Outputsig When Outen = '1' Else "Zzzzzzzz";