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Altera_Forum
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11 years ago

Gated transceiver operation on Transceiver SI Development Kit Stratix V GX board

Hi,

I have been trying to use the transceivers on the Transceiver SI Development Kit Stratix V GX board and managed to successfully use them in continuous mode. However I would like to be able to make them work in a gated mode where bits will be sent only during specific interval.

I have implemented a binary counter which I would like to use as a reference for gating the output data. The operation that I want to implement is basically to have as an output a signal that is a result of an AND operation between the 10G continuous data and the binary counter (~400ns period).

I have tried by using the reset signal, but that apparently messes up with the transceiver. I have tried to play with the assignments and allocate the output to two different transceivers (1:2 demultiplexing) but I always get some physical limitations warnings and the fitter doesn't compile successfully.

If someone has a suggestion on how to implement this or has already done it, I would appreciate your help :)

I have instantiated two .qsys systems, one as a 10G clock for triggering purposes and another one as a data channel. The top level file is the a2ch_TDM_clock.v file which I adapted from the transceiver examples.

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  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Hi Vaka,

    I would suggest that you use the mux at the core logic instead of resetting your transceiver. if you reset your transceiver, it would take time for them to restart again.
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Hi vaka,

    Agree with tiny007, the output tri-state is something to try with.

    Regarding the reset, transceiver channel would require a specific reset sequence to work. Therefore, every time you press the reset, it will go through the reset sequence where all the blocks need to be retrained. You would not be able to gate the data transmission as per your requirement.
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    To stop the data transmission at the serial output, you can tri-state the TX serial output by controlling the tx_forceelecidle input port if you are using the Custom PHY or tx_std_elecidle if you are using Native PHY. You may refer to the transceiver PHY IP user guide for further details by looking up these ports.

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Hi vaka,

    The SV transceiver is consisted of each individual and dedicated channel. So you would not be able to perform 1:2 demultiplexing. Probably you could try to send some dummy pattern ie idle pattern dring the interval where you do not want to send any data.