Gated transceiver operation on Transceiver SI Development Kit Stratix V GX board

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To stop the data transmission at the serial output, you can tri-state the TX serial output by controlling the tx_forceelecidle input port if you are using the Custom PHY or tx_std_elecidle if you are using Native PHY. You may refer to the transceiver PHY IP user guide for further details by looking up these ports.

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I was actually using the Low Latency PHY, however maybe I can try to replace the PHY and see if it will work. Thanks :)