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Altera_Forum
Honored Contributor
Honored ContributorGated Clock + Clock MUX-> what primitives to use?
Hi All, As for the Gated Clock implementation -> what primitives to use? Could someone provide examples? Thank you!
Altera_ForumHonored Contributor
Honored ContributorIf you want a reliable design, don't use gated clocks. FPGAs aren't designed to support them.
Solve it another way. Use your clock gating control signal to determine what the logic should do when it's active (clock disabled). Cheers, Alex
