Hi everybody, Does anyone know what is the delay time of a "not" gate in 40nm technology? And does anyone know what is the minimum pulse width for clock input in one FlipFlop or in one D-latch ? on which FPGA ? Also what is the minimum Time Setup and Time Hold for a single FlipFlop ? on which FPGA ? Big thanks for who may give me answers to my questions!!!!!!!:p ;) :)

Hi, I'm afraid I don't have the actual figures for you but the specs you want are dependent on quite a few variables. Firstly if you are using measuring these values in a design they may change depending on where where the logic is placed on the FPGA. e.g. setup and hold time will vary by the difference of how far the signals have to travel from where they are asserted. Temperature and process variation as well as the speed grade of the FPGA will have an effect so there is probably no one real answer. Although I'm sure people involved with Altera could probably give you a better idea. Just my 2 cents!

--- Quote Start --- Hi everybody, Does anyone know what is the delay time of a "not" gate in 40nm technology? And does anyone know what is the minimum pulse width for clock input in one FlipFlop or in one D-latch ? on which FPGA ? Also what is the minimum Time Setup and Time Hold for a single FlipFlop ? on which FPGA ? Big thanks for who may give me ansers to my questions!!!!!!!:p ;) :) --- Quote End --- Hi Shalom, what is the question behind your post ? Can you expalin a little bit more about your intentions? Kind regards GPK

Hi everybody, First of all, thank you for your answers. Behind my post I am trying to find how to delay a signal by 40-100 ps, so I make it travel throw one or more "not" gates (who have a small delay). For this I need to know what is approximatively the delay of one "not" gate on FPGA. Also I need to know what is the minimum pulse width for a clock input register on 40nm FPGA thank's for answers Shalom

Hi Shalom, Passing a signal through more gates will give you a delay, but not always the same delay for the reasons given in my first post. You may find that by chance it works for you, but any change to your source code and after a new place and route the results will almost certainly be different. To achieve what you want, you should use the timequest timing analyzer or classic if you haven't learned timequest and put in place your various constraints to achieve the timing you want. If you give some details as to what exactly you are trying to implement and why then I think people will be able to help you out more.

Shalon, due to several reasons, trying to delay a signal by adding logic cells in a FPGA is a terribly bad idea. Not only the delay of the logic cell will vary with process and temperature but you'll also have interconnect delay, which too will vary with process, temperature and your design. These add up into the >1 ns range easily. As Ardni, I sugest you provide with more information about what you're trying to do.

gate timing spec on 40nm FPGA | Altera Community

12 Replies

Altera_Forum
Honored Contributor
16 years ago
--- Quote Start ---
Hi everybody,

Does anyone know what is the delay time of a "not" gate in 40nm technology?
And does anyone know what is the minimum pulse width for clock input in one FlipFlop or in one D-latch ? on which FPGA ?
Also what is the minimum Time Setup and Time Hold for a single FlipFlop ? on which FPGA ?

Big thanks for who may give me ansers to my questions!!!!!!!:p ;) :)
--- Quote End ---

Hi Shalom,

what is the question behind your post ? Can you expalin a little bit more about your intentions?

Kind regards

GPK
Altera_Forum
Honored Contributor
16 years ago
Hi,
I'm afraid I don't have the actual figures for you but the specs you want are dependent on quite a few variables.

Firstly if you are using measuring these values in a design they may change depending on where where the logic is placed on the FPGA. e.g. setup and hold time will vary by the difference of how far the signals have to travel from where they are asserted. Temperature and process variation as well as the speed grade of the FPGA will have an effect so there is probably no one real answer. Although I'm sure people involved with Altera could probably give you a better idea.

Just my 2 cents!

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gate timing spec on 40nm FPGA

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