Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Gate Level Simulation with Modelsim

Hello, I got a problem with gate level simulation with Altera Modelsim. I have properly compiled project files Test.vho and Test_vhd.sdo. I have additionaly written a testbench in vhdl. Now in o...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

where should the path point to?

Thanks