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Altera_Forum
Honored Contributor
Honored ContributorGate Level Simulation for a specific block in the hierarchy
Hi, Lets say I have a design with a hierarchy down in the order A->B->C->D, where A is the top level, properly constrained and with proper pin settings. What I want to do, is to keep the C ...
Altera_ForumHonored Contributor
Honored ContributorHi,
you can assign ports of your C block as virtual pins in assignment editor. This way fitter will make ports of your module as a logic elements not physical device pins.
