Gate Level Simulation for a specific block in the hierarchy

Hi,

Lets say I have a design with a hierarchy down in the order A->B->C->D, where A is the top level, properly constrained and with proper pin settings.

What I want to do, is to keep the C as the top level, and to do a gate level simulation of the blocks C to D. The problem I m facing is that

C as a userlogic block has multiple ports with width = 256. Gate level simulation needs fitter to complete, as it needs timing file. Once keeping C as the toplevel file and if I compile the design, fitter fails and reports that total ports exceeds total available pins.

Any directions on how to proceed further would be quite helpful.

Regards

Jeebu Jacob Thomas