Altera_Forum
Honored Contributor
14 years agofunction error declaration in vhdl
hello guys ..i'm kind of new to this ..
i have a problem in vhdl function declaration .. i want to define function that calculate the avg of two std logic vectors .. but it keeps telling me that i have an error in the declaration .."Design unit declaration expected" here is my code : LIBRARY ieee; LIBRARY ieee_proposed; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_signed.ALL; USE ieee_proposed.std_logic_1164_additions.ALL; function avg (value1,value2 :in std_logic_vector(31 downto 0)) return std_logic_vector(31 downto 0) is variable result : std_logic_vector (31 downto 0); begin result= (value1+value2) /2; return result; end function avg; i hope anyone can help .. thnxx :)