function error declaration in vhdl

a function has to be declared inside something. So it has to be decalred inside a package, or architecture or a process. Functions do not exist on their own.

Secondly - as you're new to VHDL, may I suggest you ditch std_logic_signed - it is a non-standard package. std_logic_vectors are not meant to represent numbers. VHDL is strongly typed, and has unsigned and signed types to deal with numeric vectors inside the numeric_std package (which is part of the VHDL standard).