Honored Contributor
Honored ContributorI'm afraid 3.3V on VCC_CKLK doesn't sound right. Your -3 part doesn't support the ClockLock/ClockBoost circuit and PLL for which this pin is relevant. I assume you're not using the PLL (which I don't believe your device has)? In which case this pin should be connected to VCCINT - 2.5V. I doubt that's the cause of your issue. However, it could result in damage to the FPGA.
I'm not sure I understand your description of your circuit topology. Does your CBUS4 signal feed both FPGA pins 125 & 126? If so, that shouldn't be much of a problem. However, I'd recommend it only feeds one of the dedicated clock pins - 55 or 125. That's enough to allow you to generate your divided clocks - there's no need to feed the signal to an additional pin. --- Quote Start --- my clock is there but seams to be unstable --- Quote End --- Can you lift the FTDI pin, such that it's not being loaded, and see what the clock looks like? It should be perfect. Assuming so then something in your circuit is loading it too much. --- Quote Start --- I want to divide my clock by 4 (48/4= 12Mhz) and send it to pin 55 --- Quote End --- Pin 55 is a dedicated input pin. So, you can't feed a generated clock signal out of it. If you want to feed it out of the FPGA you'll need to use another pin. --- Quote Start --- I assumed the fpga input needed a pull-up? --- Quote End --- No. That's not the (necessarily) case. If your clock source can go tri-state then a pull-up could be considered good practice to ensure the FPGA doesn't misbehave. However, a 10kR resistor, or higher, would be sufficient. Cheers, Alex
